? semiconductor components industries, llc, 2001 april, 2001 rev. 2 1 publication order number: mc10ep90/d mc10ep90, mc100ep90 -3.3v / -5vtriple ecl input to lvpecl/pecl output translator the mc10/100ep90 is a triple ecl to lvpecl/pecl translator. the device receives differential lvecl or ecl signals and translates them to differential lvpecl or pecl output signals. a v bb output is provided for interfacing with single ended lvecl or ecl signals at the input. if a single ended input is to be used the v bb output should be connected to the d input. the active signal would then drive the d input. when used the v bb output should be bypassed to ground by a 0.01 m f capacitor. the v bb output is designed to act as the switching reference for the ep90 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5 ma of current. to accomplish the level translation the ep90 requires three power rails. the v cc supply should be connected to the positive supply, and the v ee connected to the negative supply. the 100 series contains temperature compensation. ? 260 ps typical propagation delay ? maximum frequency > 3 ghz typical ? voltage supplies v cc = 3.0 v to 5.5 v, v ee = 3.0 v to 5.5 v, gnd = 0 v ? open input default state ? safety clamp on inputs ? fully differential design ? q output will default low with inputs open or at v ee ? v bb output tssop20 dt suffix case 948e http://onsemi.com device package shipping ordering information mc10ep90dt tssop20 75 units/rail mc10ep90dtr2 tssop20 2500 tape & reel marking diagram* xxx = mc10 or 100 a = assembly location l = wafer lot y = year w = work week *for additional information, see application note and8002/d mc100ep90dt tssop20 75 units/rail mc100ep90dtr2 tssop20 2500 tape & reel xxxx ep90 alyw 1 20 20 1
mc10ep90, mc100ep90 http://onsemi.com 2 d1 d0 d2 v bb 17 18 16 15 14 13 12 4 3 5678 9 q0 11 10 gnd q1 gnd q2 q2 v cc d0 19 20 2 1 v cc q0 d1 v cc v bb v ee d2 q1 lvpecl/ pecl ecl lvpecl/ pecl ecl lvpecl/ pecl ecl pin description pin q(0:2), q (0:2) d(0:2)*, d (0:2)* differential lvecl or ecl inputs function differential lvpecl or pecl outputs v cc gnd ground positive supply v ee v bb output reference supply negative supply 5v ecl to 5v pecl 5v ecl to 3.3v pecl 3.3v ecl to 5v pecl 3.3v ecl to 3.3v pecl function table 5 v 3.3 v 5 v 3.3 v 0 v 0 v 0 v 0 v 5 v 5 v 3.3 v 3.3 v function v cc v ee gnd warning: all v cc , v ee and gnd pins must be externally connected to power supply to guarantee proper operation. figure 1. 20lead tssop (top view) and logic diagram * pins will default low when left open. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1.) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 350 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. maximum ratings (note 2.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply gnd = 0 v 6 v v ee necl mode power supply gnd = 0 v 6 v v i pecl mode input volta g e gnd = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage gnd = 0 v gnd = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 20 tssop 20 tssop 140 100 c/w c/w q jc thermal resistance (junction to case) std bd 20 tssop 23 to 41 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
mc10ep90, mc100ep90 http://onsemi.com 3 10ep dc characteristics v cc = 3.3 v, v ee = 5.5v to 3.0v; gnd = 0 v (note 3.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 5 13 20 5 13 20 5 13 20 ma i cc positive power supply current 43 55 67 43 55 67 43 55 67 ma v oh output high voltage (note 4.) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 4.) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (single ended) 1210 885 1145 820 1085 760 mv v il input low voltage (single ended) 1935 1610 1870 1545 1810 1485 mv v bb output voltage reference 1510 1410 1310 1445 1345 1245 1385 1285 1185 mv v ihcmr input high voltage common mode range (differential) (note 5.) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: 10ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . 4. all loading with 50 ohms to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 10ep dc characteristics v cc = 5.0 v, v ee = 5.5v to 3.0v; gnd = 0 v (note 6.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 5 13 20 5 13 20 5 13 20 ma i cc positive power supply current 43 55 67 43 55 67 43 55 67 ma v oh output high voltage (note 7.) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 7.) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (single ended) 1210 885 1145 820 1085 760 mv v il input low voltage (single ended) 1935 1690 1870 1545 1810 1485 mv v bb output voltage reference 1510 1410 1310 1445 1345 1245 1385 1285 1185 mv v ihcmr input high voltage common mode range (differential) (note 8.) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: 10ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . 7. all loading with 50 ohms to v cc 2.0 volts. 8. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
mc10ep90, mc100ep90 http://onsemi.com 4 100ep dc characteristics v cc = 3.3 v, v ee = 5.5v to 3.0v; gnd = 0 v (note 9.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 5 13 20 5 13 20 5 13 20 ma i cc positive power supply current 45 58 70 50 62 75 53 65 78 ma v oh output high voltage (note 10.) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 10.) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (single ended) 1210 885 1145 820 1085 760 mv v il input low voltage (single ended) 1935 1610 1870 1545 1810 1485 mv v bb output voltage reference 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 11.) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: 100ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. th e circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . 10. all loading with 50 ohms to v cc 2.0 volts. 11. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 100ep dc characteristics v cc = 5.0 v, v ee = 5.5v to 3.0v; gnd = 0 v (note 12.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 5 13 20 5 13 20 5 13 20 ma i cc positive power supply current 45 58 70 50 62 75 53 65 78 ma v oh output high voltage (note 13.) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 13.) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (single ended) 1210 885 1145 820 1085 760 mv v il input low voltage (single ended) 1935 1610 1870 1545 1810 1485 mv v bb output voltage reference 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 14.) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: 100ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. th e circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. input and output parameters vary 1:1 with v cc . 13. all loading with 50 ohms to v cc 2.0 volts. 14. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .. the v ihcmr range is referenced to the most positive side of the differential input signal.
mc10ep90, mc100ep90 http://onsemi.com 5 ac characteristics v ee = 3.0 v to 5.5 v; v cc = 3.0 v to 5.5 v; gnd = 0 v (note 15.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 2 f max /jitter) > 3 > 3 > 3 ghz t plh , t phl propagation delay to output differential 170 240 310 200 260 340 230 300 370 ps t skew duty cycle skew (note 16.) 5.0 20 5.0 20 5.0 20 ps skew within device skew q, q device to device skew (note 16.) 80 140 80 140 80 140 t jitter cycletocycle jitter (see figure 2 f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (diff.) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times q, q (20% 80%) 70 120 170 80 130 180 100 150 230 ps 15. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc 2.0 v. 16. skew is measured between outputs under identical transitions. duty cycle skew is defined only for differential operation whe n the delays are measured from the cross point of the inputs to the cross point of the outputs. 0 100 200 300 400 500 600 700 800 900 0 1000 2000 3000 4000 5000 figure 2. f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8 (jitter) 9 v outpp (mv) jitter out ps (rms)
mc10ep90, mc100ep90 http://onsemi.com 6 v tt = v cc 2.0 v driver device receiver device q qb d db 50 50 v tt figure 3. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices.) resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc10ep90, mc100ep90 http://onsemi.com 7 package dimensions tssop20 dt suffix plastic tssop package case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. icontrolling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-.
mc10ep90, mc100ep90 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10ep90/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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